FLVH — Silicon Neural Inference Engine

FLVH

Silicon Neural Inference Engine B3 · PCT/IB2026/053450

Neural network inference with no CPU on the data path.

An FPGA inference core triggered by a single GPIO pulse. Reads layer descriptors and weights directly from DDR via AXI4 Master. Executes multiply-accumulate in fixed-point hardware. No OS. No driver. No runtime. No jitter by design.

Architectural Invariants

These properties are guaranteed by construction — not by tuning, not statistically.

I1The CPU never participates in the data path during inference.
I2Inference is triggered exclusively by a GPIO rising edge. No other start condition exists.
I3All weights and descriptors reside in DDR — no network constants are embedded in the RTL.
I4Q16.16 accumulation does not truncate before the full layer sum is complete.
I5Silicon results are bit-exact with float64 reference on validated architectures. Delta: 0.00%.
I6Updating the deployed model requires no FPGA re-synthesis — write new DDR binaries, done.

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GPIO Trigger

Single rising edge starts inference. The engine runs to completion autonomously. No polling, no interrupt handler, no scheduler on the hot path.

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Layer Descriptor Table

32-byte descriptor per layer in DDR: geometry, addresses, activation flags. The RTL contains zero model constants. Swap the binaries, change the model.

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Q16.16 Fixed-Point MAC

64-bit accumulation prevents overflow mid-layer. Truncation only at output. Bit-exact result on every run — same input, same output, always.

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FLVH Forge Compiler

ONNX → DDR-ready binaries in under one second. Supports Conv, Gemm, BatchNorm, ReLU, MaxPool. Static overflow check before deployment.

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Auditable RTL

VHDL source. Open descriptor format. Every invariant is verifiable from the source. No black-box silicon, no opaque firmware stack.

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Platform Portable

Validated on Zynq-7020 (Arty Z7-20, <$200). Porting to AMD Kria KV260 (ZU5EV) in progress. Architecture-independent invariants survive every port.

Validated Results — Physical Silicon

All measurements on Digilent Arty Z7-20 (XC7Z020CLG400-1). No simulation. No emulation.

Metric

MLP 784→128→10

CNN LeNet-style

Accuracy (float64 ref)

98.05%

99.06%

Accuracy (silicon)

98.05%

99.06%

Delta float64 / silicon

0.00%

Engine latency

5 328 µs

pending KV260

Timing jitter (10k runs)

±12 µs · 0.1%

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Validation date

2026-05-12

2026-05-14/15

FLVH vs. Existing Approaches

Property

Vitis AI DPU

hls4ml / FINN

FLVH Deep Engine

CPU on data path

Yes

Model update

Redeploy Linux

Re-synthesize (4–8h)

Write DDR (<1s)

Timing jitter

Unbounded (OS)

Low

0.1% by construction

Auditable RTL

Yes

Open hardware

Yes

Yes (<$200)

Licensing · Partnership · Integration

FLVH Deep Engine is available for licensing under PCT/IB2026/053450.
Display industry · Industrial control · Embedded medical · Automotive edge AI.

Contact for Licensing →